Hackaday

Teach Yourself Verilog With This Tiny CPU Design

You probably couldn’t write a decent novel if you’d never read a novel. Learning to do something often involves studying what other people did before you. One problem with trying to learn new ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Hackaday

Breathing LED Done With Raw Logic Synthesized From A Verilog Design

Breathing LEDs are an attractive adornment on many electronic devices. These days they’re typically controlled by software but of course there were fading effects back in the days of analog too.
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Design-Reuse

System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study

This document discusses Random constraint-based verification and explains how random verification can complement the directed verification for the generic designs. In our case this is demonstrated by ...
EDN

Simulating mixed-mode designs with Verilog-only models

As the capacities of today's chips grow and their geometries shrink, specialized clock-generation circuits are necessary to reduce electrical-magnetic emissions. One scheme that is gaining industry ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Electronics Weekly

Design tool converts Verilog descriptions into C

A Cambridge firm has developed a tool that converts a Verilog description of hardware into C. Tenison EDA said its VTOC tool will allow designers to make efficient C models of their hardware, speeding ...