Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
Hackaday

FPGAs In C With Cynth

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a ...
Hosted on MSN

Engineers create first AI model specialized for chip design language

Researchers at NYU Tandon School of Engineering have created VeriGen, the first specialized artificial intelligence model successfully trained to generate Verilog code, the programming language that ...
Electronics Weekly

Design tool converts Verilog descriptions into C

A Cambridge firm has developed a tool that converts a Verilog description of hardware into C. Tenison EDA said its VTOC tool will allow designers to make efficient C models of their hardware, speeding ...
EDN

SynaptiCAD’s V2V Translators get Verilog 2001 Support and Graphical Debugger

SynaptiCAD has released a new version of it’s V2V tools for translating between VHDL and Verilog source code that supports Verilog 2001 code constructs. Also, SynaptiCAD’s BugHunter Pro can now be ...
EDN

Aldec claims Verilog simulation speedup

HENDERSON, Nev. — For most IC designers, logic simulation can never be fast enough. Aldec Corp. is paying attention, and is claiming that its new Riviera-Pro 2006.10 HDL simulator provides a 57 ...