Agilent Technologies has announced a strategic partnership with Aster Technologies to enable integration of Aster's TestWay Coverage Analyst with Agilent's printed-circuit-board assembly-test ...

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult ...

February 5, 2013. ASTER Technologies, a supplier of board-level testability and test-coverage analysis products, has developed a new release of TestWay in support of “Design for Excellence” (DfX) ...

The growth in safety-critical applications has ushered in a paradigm shift in automotive IC functional safety and test coverage analysis. The increased need for safety, low defect rate, and long-term ...

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...

Back in the day, we'd write some code, compile, execute, see what happened and repeat. That was testing. (Sometimes that's still what testing looks like, for better or worse.) Today, we can do a lot ...