Electronic Design

Expanded Role for JTAG DFT

In recent years, boundary scan has transformed itself. JTAG started more than a decade ago as a simple structural interconnect test technology. It now is a foundational embedded infrastructure capable ...
EDN

Partitioning extends utility of JTAG scan chains

– Extend the IEEE 1149.1 Test Bus into a Multi-drop Backplane Environment (This allows cards to be removed from the backplane without breaking the JTAG chain) – A Mode Register Allows Local TAPS to be ...
EDN

Testing and Debugging DSP Systems, Part 2

Part one introduces the hardware used for debugging, the debugging challenges facing DSP programmers, and debugging methodologies.Part three explains how emulators control programs on the DSP through ...
Embedded

Using an open debug interconnect model to simplify embedded systems design

Technology people are generally familiar with the Open SystemsInterconnection model for computer networks and protocols, oftenreferred to as the OSIReference Model (ISO 7498)[1].The Basic Reference ...
Electronic Design

Testing: Boundary Scan Style

Maybe you should try boundary scan testing now that your continuity buzzer has died. Most engineers are familiar with the theory of boundary scan testing, but what about having actual hands-on ...