Semiconductor Engineering

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)

A new technical paper titled “CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing” was published by researchers at University of California, Riverside. “Secure ...
Nature

Hardware Architecture for Cryptographic Algorithms on FPGA

Field Programmable Gate Arrays (FPGAs) have emerged as a versatile platform for implementing cryptographic algorithms, offering a balance between flexibility, performance and energy efficiency. Recent ...
Semiconductor Engineering

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)

“In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ...
Liliputing

NXP i.MX 95 chips feature up to 6 Cortex-A55 cores, an AI accelerator and 10 GbE Ethernet support

Chip maker NXP has unveiled a new line of processors designed for automotive, industrial, networking, connectivity, and other applications. The NXP i.MX 95 family or chips combine up to six ARM Cortex ...
PR Newswire

Gateworks joins forces with NXP to unveil new USA-made M.2 AI acceleration card, featuring decoupled AI architecture

In collaboration with NXP, Gateworks is releasing a new M.2 AI Acceleration Card, the GW16168, with NXP's passively cooled Discrete NPU (DNPU), the Ara240. Designed, tested and assembled in the USA, ...